Digital Electronics And Logic Design

  The Shift Register The Shift Register is another type of sequential logic circuit that can be used for the storage or the transfer of binary data This sequential device loads the data present on its inputs and then moves or “shifts” it to its output once every clock cycle, hence the name  Shift Register . A  shift register  basically consists of several single bit “D-Type Data Latches”, one for each data bit, either a logic “0” or a “1”, connected together in a serial type daisy-chain arrangement so that the output from one data latch becomes the input of the next latch and so on. Data bits may be fed in or out of a shift register serially, that is one after the other from either the left or the right direction, or all together at the same time in a parallel configuration. The number of individual data latches required to make up a single  Shift Register  device is usually determined by the number of bits to be stored with the most common being 8-bits (one byte) wide constructed from

The D-type Flip Flop The D-type flip-flop is a modified Set-Reset flip-flop with the addition of an inverter to prevent the S and R inputs from being at the same logic level One of the main disadvantages of the basic  SR NAND Gate Bistable  circuit is that the indeterminate input condition of SET = “0” and RESET = “0” is forbidden. This state will force both outputs to be at logic “1”, overriding the feedback latching action and whichever input goes to logic level “1” first will lose control, while the other input still at logic “0” controls the resulting state of the latch. But in order to prevent this from happening an inverter can be connected between the “SET” and the “RESET” inputs to produce another type of flip flop circuit known as a  Data Latch ,  Delay flip flop ,  D-type Bistable ,  D-type Flip Flop  or just simply a  D Flip Flop  as it is more generally called. The  D Flip Flop  is by far the most important of all the clocked flip-flops. By adding an inverter (NOT

  The JK Flip Flop The JK Flip-flop is similar to the SR Flip-flop but there is no change in state when the J and K inputs are both LOW The basic S-R NAND flip-flop circuit has many advantages and uses in sequential logic circuits but it suffers from two basic switching problems. 1. the Set = 0 and Reset = 0 condition (S = R = 0) must always be avoided 2. if Set or Reset change state while the enable (EN) input is high the correct latching action may not occur Then to overcome these two fundamental design problems with the SR flip-flop design, the  JK flip Flop  was developed. This simple  JK flip Flop  is the most widely used of all the flip-flop designs and is considered to be a universal flip-flop circuit. The two inputs labelled “J” and “K” are not shortened abbreviated letters of other words, such as “S” for Set and “R” for Reset, but are themselves autonomous letters chosen by its inventor Jack Kilby to distinguish the flip-flop design from other types. The sequenti