BE Lab Manual Experiment 11

Experiment 11

Aim:-To study R-S clocked R-S, D and clocked D flip–flop.

Apparatus:- Flip – flop trainer kit, patch chords.

Theory:- A flip–flop Is a bistable electronic circuit that has two stable states i.e. its output is either 0 or +5V dc. The additional input of these gates provides a conventional means for the application of input signals to switch the flip–flop from one stable state to another. Two input NAND gates are connected to form a flip–flop circuit. These two inputs are R & S.

The flip–flop has two outputs terms as Q and. if the flip–flop is put into one state it will remain in that state as long as power is applied or until it is changed. In a digital circuit, flip–flops are used in storage, counting, sequencing and timing applications.

R-S FLIP FLOP WITHOUT CLOCK

The R–S flip–flop is the simplest. It has two inputs, S & R, and two outputs Q and. Appling the appropriate logic level to either S or R input, it will put the latch into one state or the other. When a flip–flop is set by S input, it is said by storing binary 1. (Output Q = high). When reset by R input, it is said to be storing binary 0 (output. = low).

An R–S flip–flop constructed by cross-coupling two NAND gates as shown in figure (1).

$D:\bhupesh shukla 29-01-10\D LAB\R -S.jpg$

Figure 1(b) shows the symbol of the RS flip–flop. When both R – S flip–flop input is binary 0, both Q andoutput goes high. This condition is not allowed in the normal use of flip–flop, as therepresent the complement output of Q. the truth table for R – S flip–flop is given in table 1.

Procedure:-

Study the circuit provided on the front panel of the kit.
Switch ‘ON’ the power supply.
Connect the circuit as shown in figure [1(a)] i.e. S–R flip–flop without clock, by using patch chords.
Connect Q to the output indicator circuit.
Apply the corresponding inputs and verify the truth table (1).
If necessary measure the output voltage.

Result: - Thus R–S flip–flop without clock is studied & truth table is verified.

CLOCKED R-S FLIP–FLOP:

A Clocked RS flip–flop is constructed with the help of four NAND gates to the figure 1 as shown in figure 2.

The truth table for R-S flip–flop is given in table 2.

Procedure:-

Study the circuit provided on the panel of the kit.
Switch ‘ON’ the power supply.
Now connect the circuit as shown in figure (2) i.e. S–R flip–flop with clock, by using patch chords.
Apply the corresponding inputs to S & R and apply the clock pulse.
Connect Q to the output indicator circuit.
Verify the truth table (2).
If necessary measure output voltages.

Result: - Thus R–S flip–flop with clock is studied & truth table is verified.

D FLIP –FLOP WITHOUT CLOCK:

The R–S flip–flop has two data inputs R & S. Generation of two signals to drive a flip–flop is a disadvantage in many application. Furthermore, the invalid condition of both R and S high may occur inadvertently. This has lead to the D flip–flop a circuit that needs only a single data input. Figure (3) shows the simple diagrams of the D flip–flop using NOR gate.

Circuit diagram:-

In this circuit the D input is just transferred to the output e.g. If D = 0 then the output Q is also 0 & if D = 1 output is also 1, as shown in the truth table.

Procedure:-

Study the circuit provided on the panel of the kit.
By using patch chord short the points 1 & 2 and connect output Q to output indicators circuit.
Switch ‘ON’ the power supply.
Now by giving proper input, verify the truth table 3.

Result: - Thus D flip–flop without clock is studied & truth table is verified.

CLOCKED D FLIP–FLOP:-

Figure (4) shows the simple way to build a Delay (D) flip–flop. This kind of

Circuit diagram:-

Flip–flop prevents the value of D from reaching the Q output until a clock pulse occurs.

As shown in truth table 4, while the CLK (clock) is low, D is don’t care, Q will remain latched in its last state. When the clock is high, Q takes on the last value of D. If D is changing while the clock is high, it is the last value of D that is stored.

Procedure:-