Construction of NOR gate latch and verification of its operation
Introduction
Latches are basic storage elements that operate with signal levels (rather than signal transitions). Latches controlled by a clock transition are flip-flops. Latches are edge-sensitive devices. Latches are useful for the design of the asynchronous sequential circuit.
SR (Set-Reset) Latch – SR Latch is a circuit with:
(i) 2 cross-coupled NOR gates or 2 cross-coupled NAND gates. (ii) 2 inputs S for SET and R for RESET. (iii) 2 outputs Q, Q.
The SR Latch using NOR gate is shown below with its truth table:
Figure-1:Logic Symbol of NOR gate latch Figure-2:Truth Table of NOR gate latch
While the R and S inputs are both low, feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.The R = S = 1 combination is called a restricted combination or a forbidden state because, as both NOR gates then output zeros, it breaks the logical equation Q = Q. The combination is also inappropriate in circuits where both inputs may go low simultaneously (i.e. a transition from restricted to keep). The output would lock at either 1 or 0 depending on the propagation time relations between the gates (a race condition).
Figure-3:Timing Diagram of NOR gate latch
Simulator :
Step-1) Connect the supply(+5V) to the circuit.
Step-2) Press switch 1 for input R(Reset) and switch 2 for input S(Set).
Step-3) Then press "ADD" button to add data in the given truth table and simultaneously generate the timing diagram.
Step-4) Repeat step 2 and step 3 for another set of data.
Step-5) Press the "Print" button after completing your simulation to get your results.
SEMESTER-2 nd Course: BCA SUBJECT: DIGITAL COMPUTER ORGANIZATION Syllabus : Unit-I : Digital computer and digital system; Binary number system: number base conversion. Compliments: one's, two's, 9's and 10's complements code: Gray BCD, ASCII, and error detection code. Logic Gates: AND, OR, NOT, EX-OR, Universal gate. Logic Circuit. Boolean function: Rules and simplification, simplification of Boolean function using map method, don't care condition. Unit-II: Combinational Circuits: Adders, Subtractors, Multiplexer, Demultiplexer Decoder, Encoder) Sequential Circuit: Flip-Flop: RS, Clocked RS, JK, D flip-flop, and Master board, Case studies to understand organization of laptop like Dell, Lenovo etc. slave flip-flop. Register- Introduction, Shift register, serial Transfer & parlor Load. Counters- Ripple Counter (Asynchronous), Synchronous Counters. Unit-III: 8086 internal architecture, register organization of 8086, addressing modes, instruction set and assembler ...
Quine-Mccluskey Method It also known as Tabular method. It is more systematic method of minimizing expressions of even larger number of variables. It is suitable for hand computation as well as computation by machines i.e., programmable. . The procedure is based on repeated application of the combining theorem. PA+P =P (P is set of literals) on all adjacent pairs of terms, yields the set of all PI‘s from which a minimal sum may be selected. Consider expression ∑m(0,1,4,5)= + C+A +A C First, second terms & third, fourth terms can be combined ( + ) + (C+ )= + A Reduced to ( + ) = The same result can be obtained by combining m 0 & m 4 & m 1 &m 5 in first step & resulting terms in the second step. Procedure: Decimal Representation Don‘t cares PI chart EPI Dominating Rows & Columns Determination of Minimal expressions in c...
Alternate Logic-Gate Representations We have discussed the five basic logic gates (AND, OR, INVERTER, NAND, and NOR) and the standard symbols used to represent them in a logic circuit diagram. Most of the logic networks use standard symbols. But in some networks an alternative set of symbols is used in addition to the standard symbols. The table shows the alternate set of symbols for the five basic gates. Table: Alternate Logic Gate Representations To convert any normal symbol to its corresponding alternate symbol, the following steps are used: METHODOLOGY: TO CONVERT STANDARD SYMBOL TO ALTERNATE SYMBOL Step 1: Add bubbles (indication of inversion) at those input or output points where it is not present. Step 2: Remove all pre-existing bubbles of the normal symbol, if there is any at the point (only NOT, NAND and NOR gates) Step 3: If the existing normal logic symbol is AND, change it to OR, Similarly, if it is OR, then change it to AND. There is no change for the triangular symbol of ...
to the circuit.
for input R(Reset) and switch 2 
Comments
Post a Comment