Digital Logic Families

Digital Logic Families

In Digital Designs, our primary aim is to create an Integrated Circuit (IC). A Circuit configuration or arrangement of the circuit elements in a special manner will result in a particular Logic Family. The electrical characteristics of the IC will be identical. In other words, the different parameters like Noise Margin, Fan In, Fan Out etc will be identical.

Different ICs belonging to the same logic families will be compatible with each other.

The basic Classification of the Logic Families are as follows:

• A) Bipolar Families
• B) MOS Families
• C) Hybrid Devices

A) Bipolar Families:

1. Diode Logic (DL)
2. Resistor Transistor Logic (RTL)
3. Diode Transistor Logic (DTL)
4. Transistor-Transistor Logic (TTL)
5. Emitter Coupled Logic (ECL) or Current Mode Logic (CML)
6. Integrated Injection Logic (IIL)

B) MOS Families:
1. P-MOS Family
2. N-MOS Family
3. Complementary-MOS Family

• Standard C-MOS
• Clocked C-MOS
• Bi-CMOS
• Pseudo N-MOS
• C-MOS Domino Logic
• Pass Transistor Logic

C) Hybrid Family:

• Bi-CMOS Family

Diode Logic
In DL (diode logic), only Diode and Resistors are used for implementing a particular Logic. Remember that the Diode conducts only when it is Forward Biased.

Disadvantages of Diode Logic

• Diode Logic suffers from voltage degradation from one stage to the next.
• Diode Logic only permits OR and AND functions.

Resistor Transistor Logic
In RTL (resistor transistor logic), all the logic are implemented using resistors and transistors. One basic thing about the transistor (NPN), is that HIGH at input causes output to be LOW (i.e. like an inverter). In the case of PNP transistor, the LOW at input causes output to be HIGH.

Advantage:

• Less number of Transistors

Disadvantage:

• High Power Dissipation
• Low Fan In

Diode Transistor Logic
In DTL (Diode transistor logic), all the logic is implemented using diodes and transistors.

Disadvantage:

• Propagation Delay is Larger

Transistor-Transistor Logic

In Transistor-Transistor logic or just TTL, logic gates are built only around transistors.
TTL Logic has the following sub-families:

• Standard TTL.
• High-Speed TTL
• Low Power TTL.
• Schottky TTL.
• Low Power Schottky TTL
• Advanced Schottky TTL
• Advanced Low Power Schottky TTL
• Fast Schottky

Emitter Coupled Logic
The main specialty of ECL is that it is operating in Active Region than the Saturation Region. That is the reason for its high-speed operation. As you can see in the figure, the Emitters of the Transistors Q1 and Q2 are coupled together.

Disadvantage:

• Large Silicon Area
• Large Power Consumption

Some Characteristics we consider for the selection of a particular Logic Family are:

• Supply voltage range
• Speed of response
• Power dissipation
• Input and output logic levels
• Current sourcing and sinking capability
• Fan-in
• Fan-out
• Noise margin

Introduction of Digital logic families
Miniature, low-cost electronics circuits whose components are fabricated on a single, continuous piece of semiconductor material to perform a high-level function. This IC is usually referred to as a monolithic IC first introduced in 1958. The digital ICs are categorized as,

1. Small scale integration SSI <12 no of gates
2. Medium-scale integration MSI 12 to 99 no of gates
3. Large scale integration LSI 100 to 9999 no of gates
4. Very large scale integration VLSI 10,000 or more

Bipolar ICs are devices whose active components are current-controlled while unipolar ICs are devices whose active components are voltage-controlled.
IC Packaging

1. IC packaging Protect the chip from mechanical damage and chemical contamination.
2. Provides a completed unit large enough to handle.
3. So that it is large enough for electrical connections to be made.
4. Material is molded plastic, epoxy, resin, or silicone. Ceramic used if higher thermal dissipation capabilities required. Metal/glass used in special cases.

The three most common packages for ICs are

• a) dual-in-line (DIPS) (most common)
• b) flat pack
• c) axial lead (TO5)

Characteristics of Digital ICs

Input /Output voltage level:
The following currents and voltages are specified which are very useful in the design of digital systems.

• The high-level input voltage, VIH: This is the minimum input voltage which is recognized by the gate as logic 1.
• The low-level input voltage, VIL: This is the maximum input voltage which is recognized by the gate as logic 0.
• The high-level output voltage, VOH: This is the minimum voltage available at the output corresponding to logic 1.
• The low-level output voltage, VOL: This is the maximum voltage available at the output corresponding to logic 0.
• High-level input current, IIH: This is the minimum current which must be supplied by a driving source corresponding to 1 level voltage.
• Low-level input current, IIL: This is the minimum current which must be supplied by a driving source corresponding to 0 level voltage.
• High-level output current, IOH: This is the maximum current which the gate can sink in 1 level.
• Low-level output current, IOL: This is the maximum current which the gate can sink in 0 level.
• High-level supply current, ICC (1): This is the supply current when the output of the gate is at logic 1.
• Low-level supply current, ICC (0): This is the supply current when the output of the gate is at logic (0).

Propagation Delay:

Definition: The time required for the output of a digital circuit to change states after a change at one or more of its inputs. The speed of a digital circuit is specified in terms of the propagation delay time. The delay times are measured between the 50 percent voltage levels of input and output waveforms. There are two delay times, tpHL: when the output goes from the HIGH state to the LOW state and tpLH, corresponding to the output making a transition from the LOW state to the HIGH state. The propagation delay time of the logic gate is taken as the average of these two delay times.

Fan-in

Definition: Fan-in (input load factor is the number of input signals that can be connected to a gate without causing it to operate outside its intended operating range. expressed in terms of standard inputs or units loads (ULs).

Fan-out

Defination: Fan-out (output load factor) is the maximum number of inputs that can be driven by a logic gate. A fanout of 10 means that 10 unit loads can be driven by the gate while still maintaining the output voltage within specifications for logic levels 0 and 1.

Digital IC gates are classified not only by their logic operation, but also by the specific logic circuit family to which it belongs. Each logic family has its own basic electronic circuit upon which more complex digital circuits and functions are developed.
Different types of logic gate families :

• RTL: Resistor Transistor Logic gate family
• DCTL: Direct Coupled Transistor Logic gate family
• RCTL: Resistor Capacitor Transistor Logic gate family
• DTL: Diode Transistor Logic gate family
• TTL: Transistor-Transistor logic gate family
• IIL: Integrated Injection gate family

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• CMOS and TTL Interfaces
• CMOS Logic family
• Noise Margin
• TTL Logic family

CMOS and TTL Interfaces

To achieve optimum performance in a digital system, devices from more than one logic family can be used, taking advantages of the superior characteristics of each family for different parts of the system. For example, CMOS logic ICs can be used in those parts of the system where low power dissipation is required, whereas TTL can be used for those portions of the system which require high speed of operation. Also, some function may be easily available in TTL and others may be available in CMOS. Therefore, it is necessary to examine the interface between CMOS and TTL devices.
CMOS and TTL are the two most widely used logic families. Although ICs belonging to the same logic family have no special interface requirements, that is, the output of one can directly feed the input of the other, the same is not true if we have to interconnect digital ICs belonging to different logic families. Incompatibility of ICs belonging to different families mainly arises from different voltage levels and current requirements associated with LOW and HIGH logic states at the inputs and outputs.
CMOS driving TTL:
Following figure shows a CMOS gate driving N TTL gates. For such an arrangement to operate properly the following conditions are required to be satisfied,

VOH (CMOS) ≥ VIH(TTL)

VOL (CMOS) ≤ VIL(TTL)

– IOH (CMOS) ≥ NIIH(TTL)

IOL (CMOS) ≥ – NIIL(TTL)

The first possible type of CMOS-to-TTL interface is the one where both ICs are operated from a common supply. We have read in earlier sections that the TTL family has a recommended supply voltage of 5 V, whereas the CMOS family devices can operate over a wide supply voltage range of 3–18 V. In the present case, both ICs would operate from 5 V. As far as the voltage levels in the two logic states are concerned, the two have become compatible. The CMOS output has a VOH(min.) of 4.95V (for VCC =5 V) and a VOL(max.) of 0.05 V, which is compatible with VIH(min.) and VIL(max.) requirements of approximately 2 and 0.8V respectively for TTL family devices. In fact, in a CMOS-to- TTL interface, with the two devices operating on the same VCC, voltage level compatibility is always there. It is the current level compatibility that needs attention. That is, in the LOW state, the output current-sinking capability of the CMOS IC in question must at least equal the input current-sinking requirement of the TTL IC being driven. Similarly, in the HIGH state, the HIGH output current drive capability of the CMOS IC must equal or exceed the HIGH-level input current requirement of TTL IC. For a proper interface, both the above conditions must be met. As a rule of thumb, a CMOS IC belonging to the 4000B family (the most widely used CMOS family) can feed one LS TTL or two low-power TTL unit loads. When a CMOS IC needs to drive a standard TTL or a Schottky TTL device, a CMOS buffer (4049B or 4050B) is used. 4049B and 4050B are hex buffers of inverting and noninverting types respectively, with each buffer capable of driving two standard TTL loads.

Figure below shows a CMOS-to-TTL interface with both devices operating from 5V supply and the CMOS IC driving a low-power TTL or a low-power Schottky TTL device.

Figure below shows a CMOS-to-TTL interface where the TTL device in use is either a standard TTL or a Schottky TTL.

The CMOS-to-TTL interface when the two are operating on different power supply voltages can be achieved in several ways. One such scheme is shown below. In this case, there is both a voltage level as well as a current level compatibility problem.

TTL Driving CMOS :
For TTL gate driving N CMOS gates arrangement to operate properly, the following conditions are required to be satisfied:

VOH (TTL) ≥ VIH(CMOS)

VOL (TTL) ≤ VIL(CMOS)

– IOH (TTL) ≥ NIIH(CMOS)

IOL (TTL) ≥ – NIIL(CMOS)

In the TTL-to-CMOS interface, current compatibility is always there. The voltage level compatibility in the two states is a problem. VOH (min.) of TTL devices is too low as regards the VIH (min.) requirement of CMOS devices. When the two devices are operating on the same power supply voltage, that is, 5 V, a pull-up resistor of 10 k_ achieves compatibility as shown in below figure.

The pull-up resistor causes the TTL output to rise to about 5V when HIGH. When the two are operating on different power supplies, one of the simplest interface techniques is to use a transistor (as a switch) in-between the two, as shown below.

Another technique is to use an open collector type TTL buffer as shown below.

 

Noise Margin

Definition: Ability of the gate to tolerate fluctuations of the voltage levels.The input and output voltage levels defined above point. Stray electric and magnetic fields may induce unwanted voltages, known as noise, on the connecting wires between logic circuits. This may cause the voltage at the input to a logic circuit to drop below VIH or rise above VIL and may produce undesired operation. The circuit's ability to tolerate noise signals is referred to as the noise immunity, a quantitative measure of which is called noise margin.
The noise margins defined above are referred to as dc noise margins. Strictly speaking, the noise is generally thought of as an a.c. signal with amplitude and pulse width. For high speed ICs, a pulse width of a few microseconds is extremely long in comparison to the propagation delay time of the circuit and therefore, treated as d.c. as far as the response of the logic circuit is concerned. As the noise pulse width decreases and approaches the propagation delay time of the circuit, the pulse duration is too short for the circuit to respond. Under this condition, a large pulse amplitude would be required to produce a change in the circuit output. This means that a logic circuit can effectively tolerate a large noise amplitude if the noise is of a very short duration. This is referred to as ac noise margin and is substantially greater than the dc noise margin. It is generally supplied by the manufacturers in the form of a curve between noise margin and noise pulse width.

• VNH = HIGH-state noise margin
• VNL = LOW-state noise margin
• VIL = LOW-state input voltage
• VIH = HIGH-state input voltage
• VOL = LOW-state output voltage
• VOH = HIGh-state output voltage

Where,

• VNH = VOH -VIH
• VNL = VIL – VOL

See below Figure to calculate noise margin

Manufacturers specify voltage limits to represent the logical 0 or 1. These limits are not the same at the input and output sides. For example, a particular gate A may output a voltage of 4.8V when it is supposed to output a HIGH but, at its input side, it can take a voltage of 3V as HIGH. In this way, if any noise should corrupt the signal, there is some margin for error.

Power- Delay Product in CMOS

Power- Delay Product in CMOS :

The power-delay product (PDP) is defined as a product of power dissipation and the propagation delay. Figure below shows the shows the PDP input signal waveform.

Fig1-Power-Delay-Product-in-CMOS

PDP = Pav tp

The PDP presents a measure of energy, as is apparent from the units (Wsec = Joule).

Assuming that the gate is switched at its maximum possible rate of fmax = 1 /2 tp and ignoring the contributions of the static and direct path currents to the power consumption, we find

PDP = CLV2DD fmax tp = CLV2DD2

The PDP indicates the average energy consumed per switching event (this is, for a

0  1, or 1  0 transition). The power delay product (PDP) is mainly used to determine the performance of a digital integrated circuit.

In order to understand the meaning of the PDP, consider square wave Vin(t)

is applied to the CMOS Inverter; the output voltage Vout(t) then can be drawn in the Figure.The average propagation delay is,

tPHL  D = Ron Cout

tPLH  L = RL Cout

tP  1/2 (Ron + RL)Cout average propagation delay

Current flows only during a switching event so the average current in a logic cycle T can be written as

Iav = 1T [IDn LHtLH + IDn , HLtHL]

In this equation

IDn ,LH  1tLH tLH0 IDn(t)dt.

gives the average current during the rise time while

IDn,HL  1tHL tLH0 IDn(t)dt

is the average fall time current. For a completely symmetric CMOS inverter

IDn,LH = IDHL = IDn,av, So the power-delay product is given by

PDOCMOS = IDn,av VDDtp ffmax

Fig2-Power-Delay-Product-in-CMOS

Power Dissipation minimization Techniques

Power Dissipation minimization Techniques :

• In order to minimize the power dissipation in digital integrated circuits three techniques are used. 1) Voltage Scaling 2) Clock Frequency Reduction and 3) Switched Capacitance Reduction. In voltage scaling the supply voltage is reduced.
• As the dynamic power dissipation and short circuit power dissipation are dependent on power supply voltage, reducing the power supply voltage reduces the power dissipation. In clock frequency reduction technique the clock frequency of the processors is reduced.
• Reducing clock frequency is not leads to efficient power reduction. But, since processors are having power down modes, the clock signal are not used in the modes which leads to reduction in power dissipation.
• In switched capacitance reduction, reducing the switched capacitance is helpful to reduce the clock frequency.

Total Power Consumption of CMOS Inverter :

Now, by considering all the power dissipation components i.e. dynamic power dissipation, power dissipation in direct current paths and static power dissipation, the total power dissipation is given by,

		Ptotal	=	Pdynamic + Pdp  + Pstatic		  
			=	CL VDD2 f + tdp * VDD * Ip * f + Ileakage VDD 
			=	(CLVDD2 +  tdp * VDD * IP) f + Ileakage VDD

Digital Logic Familys Quiz
1. In general the
propagation delay time of MOS devices _________ .
a) Is of the same order as bipolar devices
b) Is less than those of bipolar devices
c) Is more than those bipolar devices
d) May be more or less than those of bipolar devices
2. CMOS logic consist
of ________
a) Only p-channel MOS devices
b) Only N-channel MOS devices
c) MOS devices & capacitors
d) P-channel & n-channel devices
3. MOS device are used
for VLSI because of ________
a) Their higher propagation delay
b) Higher packaging density
c) Availability of n-channel & p-channel devices
d) Availability of enhancement & depletion mode MOSFETs
4. A
CMOS inverter consists of ________ .
a) An n-channel MOSFET & a resistor
b) A p-channel MOSFET & a resistor
c) An n-channel & a p-channel MOSFETs
d) N-& p-channel MOSFETs & resistors
5. Which of the
following logic family has lowest power dissipation?
a) Low power schottky TTL
b) Standard TTL
c) CMOS
d) High power TTL
6. Wired
AND operation is possible in _________.
a) Totem-pole output
b) Open-collector
c) Open-drain output
d) b & c
7. Which
one of the following logic families can be operated using a supply voltage from
3 V to 15 V?
a) 74 TTL
b) 74 LS
c) 74 AS
d) CMOS
8. Which
has the smallest tPD?
a) TTL standard
b) ECL
c) schottky TTL
d)CMOS
























































































9. 22.Which of the following series is a TTL-IC family designed to operate satisfactorily in the temperature range from -550C to +1250C for military applications?
a) 5300 series
c) 7300 series
b) 5400 series
d) 7400 series